integrated circuit systems, inc. general description features ics2510c block diagram 3.3v phase-lock loop clock driver 2510 c rev d 06/15/01 pin configuration the ics2510c is a high performance, low skew, low jitter clock driver. it uses a phase lock loop (pll) technology to align, in both phase and frequency, the clkin signal with the clkout signal. it is specifically designed for use with synchronous sdrams. the ics2510c operates at 3.3v vcc and drives up to ten clock loads. one bank of ten outputs provide low-skew, low-jitter copies of clkin. output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at clkin. outputs can be enabled or disabled via control (oe) inputs. when the oe inputs are high, the outputs align in phase and frequency with clkin; when the oe inputs are low, the outputs are disabled to the logic low state. the ics2510c does not require external rc filter components. the loop filter for the pll is included on-chip, minimizing component count, board space, and cost. the test mode shuts off the pll and connects the input directly to the output buffer. this test mode, the ics2510c can be use as low skew fanout clock buffer device. the ics2510c comes in 24 pin 173mil thin shrink small-outline package (tssop) package. ? meets or exceeds pc133 registered dimm specification1.1 spread spectrum clock compatible distributes one clock input to one bank of ten outputs operating frequency 25mhz to 175mhz external feedback input (fbin) terminal is used to synchrionize the outputs to the clock input no external rc network required operates at 3.3v vcc plastic 24-pin 173mil tssop package fbin clkin avcc oe pll clk1 clk0 fbout clk2 clk3 clk4 clk5 clk6 clk7 clk8 clk9 agnd vcc clk0 clk1 clk2 gnd gnd clk3 clk4 vcc oe fbout clkin avcc vcc clk9 clk8 gnd gnd clk7 clk6 clk5 vcc fbin ics2510c 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 24 pin tssop 4.40 mm. body, 0.65 mm. pitch
2 ics2510c pin descriptions note: 1. weak pull-ups on these inputs pin number pin name type description 1 agnd pwr analog ground 2, 10, 14 vcc pwr power supply (3.3v) 3 clk0 out buffered clock output. 4 clk1 out buffered clock output. 5 clk2 out buffered clock output. 6, 7, 18, 19 gnd pwr ground 8 clk3 out buffered clock output. 9 clk4 out buffered clock output. 11 oe 1 in output enable (has internal pull_up). when high, normal operation. when low, clock outputs are disabled to a logic low state. 12 fbout out feedback output 13 fbin in feedback input 15 clk5 out buffered clock output. 16 clk6 out buffered clock output. 17 clk7 out buffered clock output. 20 clk8 out buffered clock output. 21 clk9 out buffered clock output. 22 vcc pwr power supply (3.3v) digital supply. 23 avcc in analog power supply (3.3v). when input is ground pll is off and bypassed. 24 clkin in cl oc k i nput functionality oe avcc clk (9:0) fbout source 03.33 0 driven pll n 13.33 driven driven pll n 00 0 driven clkin y 1 0 d r i ven dr i ven c lkin y test mode: when avcc is 0, shuts off the pll an d connec t s th e i npu t di rec tl y t o th e ou t pu t b u ff ers buffer mode inputs outputs pll shutdown
3 ics2510c absolute maximum ratings supply voltage (avcc) . . . . . . . . . . . . . . . . . . . avcc < (v cc + 0.7v) supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . 4.3 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ? 0.5 v to v cc +0.5 v ambient operating temperature . . . . . . . . . . . . 0 c to +70 c storage temperature . . . . . . . . . . . . . . . . . . . . . . ? 65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - output t a = 0 - 7 0c ; v dd = v ddl = 3 . 3 v + / - 10% ; c l = 20 - 30 pf; r l = 4 7 0 oh ms ( un l ess ot h erw i se state d) p a r a meter s ymb o l co nditi o n s min typ m a x unit s output impedance r dsp v o = v dd *(0.5) 36 ? output impedance r dsn v o = v dd *(0.5) 32 ? output high voltage v oh i oh = -8 ma 2.4 2.9 v output low voltage v ol i ol = 8 ma 0.25 0.4 v v oh = 2.4 v -26 -13.6 v oh = 2.0 v -37 -22 v ol = 0.8 v 19 25 v ol = 0.55 v 13 17 rise time 1 t r v ol = 0.8 v, v oh = 2.0 v 0.5 1.4 2.1 ns fall time 1 t f v oh = 2.0 v, v ol = 0.8 v 0.5 1.5 2.7 ns duty cycle 1 d t v t = 1.5 v;c l =30 pf 45 50 55 % at 66-100 mhz ; loaded outputs 52 100 at 133 mhz ; loaded outputs 39 75 absolute jitter 1 tjabs 10000 cycles; c l = 30 pf 57 ps skew 1 t sk v t = 1.5 v (window) output to output 80 150 ps phase error 1 t pe v t = vdd/2; clkin-fbin -150 40 150 ps phase error jitter 1 t pe 3 v t = vdd/2; clkin-fbin; delay jitter -50 35 50 ps d e l ay i nput- o utput 1 d r1 v t = 1.5 v; pll_en = 0 3.3 3.7 ns 1 guaranteed by design, not 100% tested in production. cycle to cycle jitter 1 tcyc-cyc ps output high current output low current i oh i ol ma ma
4 ics2510c symbol parameter test conditions min. max. unit fclk input clock frequency 25 175 mhz input clock frequency duty cycle 40 60 % stabilization time after power up 1 ms ti m i ng requ i remen t s over recommen d e d ranges o f supp l y voltage and operating free-air temperature note: time required for the pll circuit to obtain phase lock of its feedback signal to its reference i n or d er f or p h ase l oc k to b e o b ta i ne d , a fi xe d - f requency, fi xe d -p h ase re f erence s i gna l must b e until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not electrical characteristics - input & supply t a = 0 - 7 0c ; s upp l y vo l tage v dd = 3 . 3 v + / - 10% ( un l ess ot h erw i se state d) parameter s ymb o l co nditi o n s min typ max unit s input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 100 ua input low current i il v in = 0 v; 19 50 ua operating current i dd1 c l = 0 pf; f in @ 66m 140 170 ma input capacitance c in 1 logic inputs 4 pf output capacitance c o 1 logic outputs 8 pf 1 guarenteed by design, not 100% tested in production.
5 ics2510c parameter measurement information figure 1. load circuit for outputs notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 133 mhz, z o = 5 0 ?, t r 1. 2 n s, t f 1. 2 n s. 3. the outputs are measured one at a time with one transition per measurement. 30 pf 500 ? from output under test figure 2. voltage waveforms propagation delay times figure 3. phase error and skew calculations
6 ics2510c general layout precautions: an ics2509c is used as an example. it is similar to the ics2510c. the same rules and methods apply. 1) use copper flooded ground on the top signal layer under the clock buffer the area under u1 in figure 1 on the right is an example. 2) use power vias for power and ground. vias 20 mil or larger in diameter have lower high frequency impedance. vias for signals may be minimum drill size. 3) make all power and ground traces are as wide as the via pad for lower inductance. 4) vaa for pin 23 has a low pass rc filter to decouple the digital and analog supplies. c9-11 may be replaced with a single low esr (0.8 ohm or less) device with the same total capacitance. 5) notice that ground vias are never shared. 6) all vcc pins have a decoupling capacitor. power is always routed from the plane connection via to the capacitor pad to the vcc pin on the clock buffer. 7) component r1 is located at the clock source. component values: c1= as necessary for delay adjust c[7:2]=.01uf c8,c13=0.1uf c[11:9]=4.7uf r1=10 ohm. locate at driver r2=10 ohm. figure 1.
7 ics2510c ordering information ics2510cg-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type g=tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y g - ppp - t ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 4.40 mm. body, 0.65 mm. pitch tssop (173 mil) (0.0256 inch) index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 v ariations min max min max 24 7.70 7.90 .303 .311 10-0035 symbol in millimeters in inches common dimensions common dimensions see variations see variations 6.40 basic 0.252 basic 0.65 basic 0.0256 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153
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